4th June 13:27
An implementation of a clean reset signal
Most human-safety related requirements also include a "no single-point
failures" clause, which includes failures of any type of the clock
oscillator (no clock, fast/slow clock, etc.). Sure, there may be other
ways to handle these failures, but often the cheapest, simplest (and
all-importantly, easiest to verify/audit) method is an asynchronous
I've also designed VME interfaces in FPGAs when the only available
clock (16 MHz off the backplane) was slow enough to miss the minimum
gap between address strobes. Asynchronous reset saved the day... Not
that I recommend such approaches, but they do have their uses.
In general though, fully synchronous systems are usually easier to
verify (assuming the clock is known good!), and therefore are
preferable to asynchronous or partially asynchronous systems.