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9th April 02:17
External User
Posts: 1
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Hi all,
I am investigating programs that do automatic VHDL generating. Like there are Matlab/Simulink and LabVIEW. I have heard that there are some other tools/programs online (for free) where you can generate for instance filters from a VB.NET program. Has anyone got some links for this which he can share so I can see how those persons are implementing this? thanks in advance and Kind regards, http://www.vhdl.eu |
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9th April 02:18
External User
Posts: 1
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The company I represent, PDTi (http://www.productive-eda.com) provides
SpectaReg, a tool that generates code and docs for memory mapped registers (MMR). It captures MMR specs then can generate: * RTL implementation (verilog, vhdl) * self checking verification platform (SystemVerilog, VHDL, e, ...) * C/C++ to abstract registers/bitfields * datasheet (HTML, DocBook, DITA, Framemaker, ...) * System level C/C++ memory-map tests This enables significant efficiency improvements, reducing errors and allowing engineers to focus on value added development. Perhaps the most value comes from SpectaReg's ability to synchronize the various code and doc views with the golden spec. Certainly debugging a datasheet or software driver that doesn't match the RTL can be frustrating and time consuming-- SpectaReg eliminates this. Best Regards, Jeremy --- PDTi [ http://www.productive-eda.com ] SpectaReg -- Spec-down code and doc generation for register maps |
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