a man crying alone in the wilderness

Interesting!

My VLIW SMP MPP FORTH protocol and hardware model ( theory) ALSO use
..... a balance of four 16-bit primitives align fetched on 64-bits
boundaries, ( in my near optimal VLIW SMP MPP FORTH parallel chip
model, gand unification parallel ( multi core) chip theory)

Three 16-bit/5-bit packed instructions may be encoded within a 16-bit
instructions, the 5-bit encoded branches are hard-wired as 64-bit
relative offests in a simple relatively addressed 16-bit memory
architecture. ( 64k of 64-bit/four-16-bit words are /mostly/ addressed
ONLY using 16-bit relative branches ( of 64-bit offsets. ), indirect
calls, CLASS-BASE METHOD, CLASS-LOCAL-METHOD protocal primitive (
machine?) instructions excluded )

OBVIOUSLY, the 5-bit packed code function as similar to a Transputer's
'Type F' instruction but 31 ( thirty -one) indirectly vectored types
instead of simply one 'F' instruction, ( type of )). maw