Mombu the Programming Forum sponsored links

Go Back   Mombu the Programming Forum > Programming > plz clarify this doubt in vhdl
User Name
Password
REGISTER NOW! Mark Forums Read

sponsored links


Reply
 
1 25th April 07:31
jonathan bromley
External User
 
Posts: 1
Default plz clarify this doubt in vhdl



On 21 Sep 2006 21:39:17 -0700, "chaitanyakurmala@gmail.com"


No doubt. All variables are initialised to their leftmost value,
unless you specify otherwise. So fifo_index is unquestionably
initialised to 0 at time zero. It then retains its value across
executions of the process; it is NOT re-initialised when the
process re-starts.

Note, though, that initialisation of variables is NOT reliable in
synthesis. It is 100% ok for simulation, but synthesis usually
ignores initialisation that's part of a declaration. You need to
perform an ******** initialisation action as the result of a reset.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
  Reply With Quote


  sponsored links


Reply


Thread Tools
Display Modes




Copyright © 2006 SmartyDevil.com - Dies Mies Jeschet Boenedoesef Douvema Enitemaus -
666