25th April 07:31
plz clarify this doubt in vhdl
On 21 Sep 2006 21:39:17 -0700, "email@example.com"
No doubt. All variables are initialised to their leftmost value,
unless you specify otherwise. So fifo_index is unquestionably
initialised to 0 at time zero. It then retains its value across
executions of the process; it is NOT re-initialised when the
Note, though, that initialisation of variables is NOT reliable in
synthesis. It is 100% ok for simulation, but synthesis usually
ignores initialisation that's part of a declaration. You need to
perform an ******** initialisation action as the result of a reset.
Jonathan Bromley, Consultant
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