david bishop

This was noticed as a problem, which we plan to fix in VHDL-2006.

The basic issue was "why can't I add 1 to a std_logic_vector"? or "why
can't I convert an integer into std_logic_vector"? Std_logic_vectors
were not meant to be mathematically representations (UNSIGNED and SIGNED
were), but people use them that way anyway.

Because of this we created a package for just this situation.
We called the package "numeric_std_unsigned" (so as not to conflict with
the other names already out there).
You can get a vhdl-93 copy at:
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/numeric_std_unsigned_c.vhdl

The problem you will find with all of the non IEEE packages is that they
are different depending on which compiler you use. This new package
will be standardized, so it should be the same across all compilers.