amontec team

Hi VHDL GNU men,

Amontec is interested to build an auto-do***entation of our VHDL
libraries, cell-by-cell.

The do***entation will stay basic, like :
general description
port description
generic description
implementation description
license description
note description

The goal is to do a interface do***entation for the end-user.

Now, we know the power of XML for this kind of do***entation.
The advantage of XML is the structural view like VHDL. Having a VHDL
library do***ented in a XML format, we will be able to describe the
hardware of a SoC very quickly, and to ask XML to re-generate a VHDL
concatenated file of our XML description ... oopps)

The start-point will becomes the end-point (VHDL bottom-up design to XML
up-down design)

I will be interested if some VHDL men have a VHDL to XML parser,
thinking do***entation only.

Or is that better to do a parser to correct my VHDL libraries inserting
directly the XML format in the vhdl comment.

Let me know if some are interested to work with Amontec on this JOB.

Laurent Gauch
Amontec Team Manager
http://www.amontec.com