agatha

Hello to all of you,
I'm new to VHDL and I'm trying to understand how it works but I get to
have a little problem. I'm trying to make the data memory for a
processor. The ADDRESS consists of 32 bits but only 12 of them are
used. When I write this code:

addr := ADDRESS(11 downto 0) ;
MEMORY(TO_INTEGER(UNSIGNED(addr))) <= DATA_W(7 downto 0);

everything is all right. But when I try to align the address and write:

addr := ADDRESS(11 downto 2) & "00" ;
MEMORY( TO_INTEGER(UNSIGNED(addr))) <= DATA_W(7 downto 0);

I keep getting this warning:
Warning: 790: Index value does not match array range, simulation
mismatch

Can anyone explain what happens and it doesn't work?
Thank you in advance

mark norton

Hi,

Could you post your declarations for addr, ADDRESS, MEMORY, and DATA_W?
I think that would shed some light on the situation.

Best regards,
Mark Norton -- ==============================
Mark Norton <markn@cdvinc.com>
Concept Development, Inc.
http://www.cdvinc.com

agatha

First of all thank you for your instant reply!

This is a part of the code:
entity MEMORY4 is
port( DATA_A: out STD_LOGIC_VECTOR (31downto 0);
DATA_W: in STD_LOGIC_VECTOR (31downto 0);
ADDRESS: in STD_LOGIC_VECTOR(31downto 0);

ENABLE_A: in STD_LOGIC;
ENABLE_W: in STD_LOGIC;
W_LEN: in STD_LOGIC_VECTOR(1 downto 0);

REQ: in STD_LOGIC;
ACK: out STD_LOGIC;
CLK: in STD_LOGIC);
end MEMORY4;
....
architecture synthesis of MEMORY4 is

type MEM is array ((2**12 - 1) downto 0) of STD_LOGIC_VECTOR(7downto
0);
signal MEMORY:MEM ;

process (CLK)

variable addr: STD_LOGIC_VECTOR(11 downto 0);

begin
addr := ADDRESS(11 downto 2) & "00";

if ENABLE_W = '1' then
MEMORY( TO_INTEGER(UNSIGNED(addr))) <= DATA_W(7 downto 0);
.....

The memory consists of 2**12 positions and every position is one byte.
When I get the address that is 32 bits I must consider only the lower
12 (11 downto 0) and save the data, that is also 32 bits, to 4
positions of the memory, one byte at a time. That's why I must align

Maybe the situation is more clear now.

phoenix

Dnia 23-05-2006 o 18:43:14 agatha <vivi01402@hotmail.com> napisa³:

Hello

Maybe it is something wrong with concatenation use in variable assign and
maybe You should try:

addr(11 downto 2) := ADDRESS(11 downto 2);
addr(1 downto 0) := "00";

agatha

I tried it now but the warning is still there!! The thing is I don't
know any possible reason for it's appearance and I don't know if I
should ignore it or not.

phoenix

Dnia 23-05-2006 o 19:16:43 agatha <vivi01402@hotmail.com> napisa³:

This is warning, that you may try ignore it and, if simulation works then
check what the memory behaviour is.
Or maybe try change variable addr to signal and then use the "<=" assign?

agatha

You were right!! I changed the variable to a signal and put it out of
the process and the warning was gone!
Thank you very much!!!

paulo dutra

Is it because you did not specify the base designator
addr := ADDRESS(11 downto 2) & B"00" ;

Otherwise, I believe it's assumed to be hex.
addr := ADDRESS(11 downto 2) & X"00" ;

phoenix

Dnia 23-05-2006 o 20:03:38 agatha <vivi01402@hotmail.com> napisa³:

No problem

mark norton

No, for most instances, "00" would be just two bits.

However, I think the issue is that array indices need to be locally
static. So the solution of changing it to a signal that operated
outside the process solved that. The prior example that worked would
probably have synthesized the variable right out of the process since it
was a 1-to-1 assignment to the input (my best guess right now).

Best regards,
Mark Norton

-- ==============================
Mark Norton <markn@cdvinc.com>
Concept Development, Inc.
http://www.cdvinc.com